Such a semiconductor device installed in an IC card is known that its security is high because its internal secret data is processed without being released to the outside. An attack of accessing and reading the internal data in the high security semiconductor device from the outside is commonly classified into destructive analysis and non-destructive analysis.
The destructive analysis is designed for physically modifying a semiconductor device to read out or rewrite its internal data. In the destructive analysis, information about a device for modifying and circuit of the semiconductor device to be examined is required, analysis takes a considerable length of time and a significant amount of cost and an attack hardly be implemented with success.
In contrast, the non-destructive analysis is intended for attacking its action without physically modifying the semiconductor device.
The non-destructive analysis is also substantially classified into Differential Fault Analysis (DFA), in which an error is induced and secret data are exposed by providing an terminal of a semiconductor device with noise or providing an operation environment of a semiconductor device with stress, Simple Power Analysis (SPA) and Differential Power Analysis (DPA), in both which secret data are exposed by analyzing a power consumption of a semiconductor device, examining an internal action and then estimating the internal action. While, the attack by DFA is possibly inhibited using sensors which monitor the outside environment, the attack by the power consumption analysis can hardly be monitored by the semiconductor device. Accordingly, any type of the semiconductor device having no counter measure against the power consumption analysis is disadvantageous on its security.
There is a technique for providing the action clock at random for the security concerns in the power consumption analysis (See Patent Citation 1). Patent Citation 1 employs a pseudo random number sequence as the clock for a sub module in the internal circuit. This permits processing time and power consumption for the same process in the sub module to be varied at each action, and thus the power consumption analysis becomes difficult.
FIG. 7 is a block diagram showing a circuit used by the technique disclosed in Patent Citation 1. Patent Citation 1 discloses a semiconductor device 100 which comprises an input clock signal 110 and a pair of clock converting circuits 101 and 121 for converting and outputting the input clock signal, where the input clock signal 110 is converted by the action of the clock converting circuits 101 and 121 into clock signals of pseudo random number sequence which are used by sub modules in modules 108 and 109. Accordingly, the power consumption appears at random regardless of the internal processing of the circuit and thus the power consumption analysis becomes difficult.    [Patent Citation 1]: Japanese Patent Laid-open Publication No. 2003-337750.